1. CALL FOR PAPERS
    R T C S A
    THE 23RD IEEE INTERNATIONAL CONFERENCE ON EMBEDDED
    AND REAL-TIME COMPUTING SYSTEMS AND APPLICATIONS
    August 16-18, 2017, Hsinchu, Taiwan


    Important Dates:
    - Paper Submission Deadline: April 14, 2017
    - Acceptance Notification: June 2, 2017
    - Final Paper Submission: June 16, 2017
    - Conference Date: August 16-18, 2017

    RTCSA 2017 is going to be held in Hsinchu, Taiwan and organized by NCTU. The RTCSA conference series carry on with the tradition and bring together researchers and developers from academia and industry for advancing the technology of embedded and real-time systems and their emerging applications, including the Internet of things and cyber-physical systems.

    RTCSA seeks both research and industry track papers that describe research or technical aspects in the area of embedded and real-time systems. Proceedings will be published by the IEEE Computer Society. More information on RTCSA 2017 can be found at http://www.rtcsa.org/

    [Sponsors]
    IEEE Computer Society Technical Committee of Real-Time Systems, IEEE Technical Committee on Cyber-Physical Systems, and Computer Society of the Republic of China.

    [Scopes]
    The 23rd edition of RTCSA will bring together researchers and developers from academia and industry to promote cross-fertilization and discuss advances and trends in the technology of embedded and real-time systems and their emerging applications, including the Internet of Things and Cyber-Physical Systems. RTCSA 2017 seeks
    papers that describe original research in these areas, particularly in:

    **************************
    * EMBEDDED SYSTEMS TRACK *
    **************************
    - Embedded System Architectures
    - Multi-Core Embedded Systems
    - Operating Systems and Scheduling
    - Embedded Software and Compilers
    - Non-Voltaile Memory and Storage
    - Power/Thermal Aware Design
    - Fault Tolerance and Security
    - Sensor-based Systems and Applications
    - Embedded Systems and Design Methods for Cyber-Physical Systems
    - Reconfigurable Computing Architectures and Software Support
    - Ubiquitous and Distributed Embedded Systems and Networks

    ***************************
    * REAL-TIME SYSTEMS TRACK *
    ***************************
    - Real-Time Operating Systems
    - Real-Time Scheduling
    - Timing Analysis
    - Programming Languages and Run-Time Systems
    - Middleware Systems
    - Design and Analysis Tools
    - Communication Networks and Protocols
    - Media Processing and Transmissions
    - Real-Time Aspects of Wireless Sensor Networks
    - Energy Aware Real-Time Methods
    - Real-Time Aspects of Databases

    *********************************************
    * IoT, CPS, AND EMERGING APPLICATIONS TRACK *
    *********************************************
    - Systems, Technology and Foundations of IoT and CPS
    - Applications and Case Studies of IoT and CPS
    - Smart and Connected Health
    - Industrial Internet and Industry 4.0
    - Smart City Technology and Applications
    - Smart Transportation and Infrastructure
    - Cyber-Physical Co-Design
    - Cloud, Middleware and Networks for IoT and CPS
    - Wireless Sensor-Actuator Networks for IoT and CPS
    - Industrial Networks and Systems

    RTCSA 2017 General Chairs:
    - Samarjit Chakraborty, TU Munich, Germany
    - Li-Pin Chang, National Chiao-Tung University, Taiwan

    RTCSA 2017 Program Chairs:
    - Real-Time Systems Track: Bjorn Andersson, CMU, USA
    - Embedded Systems Track: Jen-Wei Hsieh, National Taiwan University of Science and Technology, Taiwan
    - IoT, CPS, and Emerging Applications Track: Luis Almeida, U. Porto, Portugal

    [Paper Submission]
    Both research and industry track papers are solicited. The submitted manuscript must describe original work not previously published and not concurrently submitted elsewhere. Submissions should be no more than 10 pages in the IEEE conference proceedings format (two-column, single-space, 10pt). Conference content will be submitted for inclusion into IEEE Xplore, and will be EI indexed.

    [Work-in-Progress Session]
    This session provides an opportunity for researchers attending RTCSA to present and discuss their latest research and get early feedback from the community at large. More detailed information is available on the web.

    [Special Issues of Journals]
    Selected papers will be recommended for submission of extended versions to the special issues of journals, such as the ACM Transactions on Cyber Physical Systems (application in progress).
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  2. CALL FOR PAPERS

    Submission Deadline Extended

    24th Reconfigurable Architectures Workshop
    RAW 2017
    Buena Vista Palace Hotel
    Orlando, Florida, USA, May 29-30 2017

    QUICK LINK: Web site: http://raw.necst.it/

    IMPORTANT DATES:

    Abstract submission: February 2, 2017
    Submission deadline: February 5, 2017 (final)
    Decision notification: March 1, 2017
    Camera-Ready papers due: March 15, 2017

    The 24th Reconfigurable Architectures Workshop (RAW 2017) will be held in Orlando, Florida USA in May 2017. RAW 2017 is associated with the 31st Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2017) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.

    A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand. The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms architectures, applications, technologies and tools, is essential to
    fully exploit the possibilities offered by reconfigurable computing. The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and  practitioners in the area.


    Submissions can be made through:
    . the RAW2017 web site: http://raw.necst.it/
    . EasyChair: https://easychair.org/conferences/?conf=raw2017
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  3. Paul Caspi Award 2017


    The ACM SIGBED Paul Caspi Dissertation Award is presented annually to the author of an outstanding dissertation in the area of Embedded Systems.   Nominations are now accepted for the 2017 award.

    The nomination should be submitted via EasyChair at
           https://easychair.org/conferences/?conf=caspiaward17
    by March 1, 2016. For further information,  contact Wang.Yi@it.uu.se

    The author of the winning dissertation will be invited to publish a dissertation summary in the ACM SIGBED Newsletter and to submit their work to the journal ACM TECS (Transactions on Embedded Computing Systems) for possible publication, after the normal peer-review process. The award includes an award certificate for the author and an honorarium of 2000 USD. A public citation for the award paper will be placed on the SIGBED web site.

    Selection Committee
    Christoph Kirsch
    Nikil Dutt
    Tei-Wei Kuo
    Florence Maraninchi
    Oleg Sokolsky
    Reinhard Wilhelm
    Wang Yi (Chair)

    Selection Process

    The award is for an outstanding doctoral dissertation dated within one year preceding the nomination due date. A selection committee and a selection committee chair will be selected by the current SIGBED Executive Committee. A member of the current SIGBED Executive Committee will be one of the selection committee members. The committee chair shall adjudicate conflicts of interest, appointing substitutes to the committee as necessary. Dissertations supervised by a selection committee member are ineligible to be nominated. For purposes of continuity, committee members may remain on the committee for up to three years. The selection committee shall be no less than three persons in size.

    Nomination Process

    A nomination should consist of the following items:
       - Name, address, phone number, and email address of the person making the nomination (the nominator).
       - Name, address, phone number, and email address of the candidate for whom an award is recommended (the nominee).
       - A short statement (200-500 words) explaining why the nominee deserves the award.
       - Supporting statements from up to two persons in addition to the nominator.
       - The nominated dissertation in an English language version.
       - A list of the nominee's publications that were used as the basis of chapters in the nominated dissertation.
       - The CV of the nominee.

    The selection committee will make a recommendation on the winner of the award to the SIGBED Executive Committee, which will approve and announce the final winner. SIGBED Executive Committee members who have conflicts of interest with any nominee will be excluded from the approval process. The primary selection criterion will be the quality of the candidate's work, with the aim to recognize outstanding doctoral dissertations. The selection committee may choose to issue no award in a given year. The award may not be given to multiple recipients.


    For information about the award and the nomination process, see http://sigbed.blogspot.fr/p/awards.html
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  4. CALL FOR PAPERS

    International Symposium on Highly-Efficient Accelerators and Reconfiguration Technology

    HEART 2017

    Bochum, Germany, June 7-9, 2017

    QUICK LINK: Web site: http://heart2017.esit.rub.de/index.html

    IMPORTANT DATES:
    Paper submission due: February 20, 2017
    Author notification: April 15, 2017
    Camera-ready due: April 30, 2017
    Symposium Dates: June 7-9, 2017

    The Eighth International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART) is a forum to present and discuss new research on accelerators and the use of reconfigurable technologies for high-performance and/or power-efficient computation.
    Submissions are solicited on a wide variety of topics related to the acceleration for high-performance computation, including but not limited to:

    Architectures and systems:
    • Novel systems/platforms for efficient acceleration based on FPGA, GPU, and other devices
    • Heterogeneous processor architectures and systems for scalable, high-performance, high-reliability, and/or low-power computation
    •  Reconfigurable and configurable hardware and systems including
      IP-cores, embedded systems, SoCs, and cluster/grid/cloud computing
      systems for scalable, high-performance and/or low-power processing
    • Custom computing system for domain-specific applications such as
      Big-data, multimedia, bioinformatics, cryptography, and more
    • Novel architectures and device technologies that can be applied to efficient acceleration, including many-core/NoC architectures, 3D-stacking technologies and optical devices
    Software and applications:
    •   Novel applications of high-performance computing and Big-data processing with efficient acceleration and custom computing
    • System software, compilers and programming languages for efficient acceleration systems / platforms, including many-core processors, GPUs, FPGAs and other reconfigurable /custom processors
    • Run-time techniques for acceleration, including Just-in-Time compilation and dynamic partial-reconfiguration
    • Performance evaluation and analysis for efficient acceleration
    • High-level synthesis and design methodologies for heterogeneous, reconfigurable and/or custom processors/systems
    In order to encourage open discussion on future directions, the program committee will provide higher priority for papers that present highly innovative and challenging ideas.

    We are planning to organize special sessions on HPC, Big data, and Dynamic Reconfiguration. When submitting a paper, please select topic(s) if the paper is related to them. Note that regardless of the selection of special session topic(s), your paper will undergo the same peer-review process as the main technical track.

    Selected accepted papers will be published in ACM post-proceedings (tentative).



    FPGA Design Contest 2017 (Trax)

    Following the FPGA design competition in HEART2016, we are planning another Trax design  contest at HEART2017. The regulation of this contest will be announced soon.

    Submissions can be made through:
    . the HEART2017 web site: http://heart2017.esit.rub.de/index.html
    . EasyChair: https://easychair.org/conferences/?conf=heart2017

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  5. CALL FOR PAPERS

    24th Reconfigurable Architectures Workshop
    RAW 2017
    Buena Vista Palace Hotel
    Orlando, Florida, USA, May 29-30 2017

    QUICK LINK: Web site: http://raw.necst.it/

    IMPORTANT DATES:
    Abstract submission January 11, 2017
    Submission deadline January 15, 2017
    Decision notification  February 17, 2017

    The 24th Reconfigurable Architectures Workshop (RAW 2017) will be held in Orlando, Florida USA in May 2017. RAW 2017 is associated with the 31st Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2017) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.

    A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand. The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms architectures, applications, technologies and tools, is essential to
    fully exploit the possibilities offered by reconfigurable computing. The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and  practitioners in the area.


    Submissions can be made through:
    . the RAW2017 web site: http://raw.necst.it/
    . EasyChair: https://easychair.org/conferences/?conf=raw2017

    KEYNOTE
    Ronald F. DeMara, Director of Computer Architecture Laboratory, University of Central Florida
    Georgi Gaydadjiev, VP of Dataflow Software Engineering, Maxeler Technologies Ltd

    TOPICS OF INTEREST

    Hot Topics in Reconfigurable Computing
    • Configurable Cloud
    • Heterogeneous Computing in Data Centers
    • Accelerating Data Center Workloads
    • FPGA-based Deep Learning
    • Accelerating Genomic Computations
    • Acceleration of Data Analytics
    • Reconfigurable Computing in the IoT era
    • Organic Computing, Biology-Inspired Solutions
    • Applications in Finance

    Architectures & CAD
    • Algorithmic Techniques and Mapping
    • Emerging Technologies (optical models, 3D Interconnects, devices)
    • Reconfigurable Accelerators
    • Embedded systems and Domain-Specific solutions (Digital Media, Gaming, Automotive applications)
    • FPGA-based MPSoC and Multicore
    • Distributed Systems & Networks
    • Wireless and Mobile Systems
    • Critical issues (Security, Energy efficiency, Fault-Tolerance)

    Runtime & System Management
    • Run-Time Reconfiguration Models and Architectures
    • Autonomic computing systems
    • Operating Systems and High-Level Synthesis
    • High-Level Design Methods (Hardware/Software co-design, Compilers)
    • System Support (Soft processor programming)
    • Runtime Support
    • Reconfiguration Techniques
    • Simulations and Prototyping (performance analysis, verification tools)
    For more information see: http://raw.necst.it/
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  6. Applications for student travel grants for ESWEEK 2016 are now accepted.  See the Travel Grants page on this site for details and the application form.

    The application process is closed.  12 travel grants have been awarded.  Watch out for travel grant application announcement for CPS Week 2017.
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  7. Call for nominations: 2016 Frank Anger Memorial Award

    The ACM Special Interest Group on Embedded Systems (SIGBED) invites applications for the 2016 Frank Anger Memorial Award. 

    The Frank Anger Memorial Award is a student award in the name of late Dr. Frank Anger to promote cross-disciplinary research between embedded systems and software engineering.  The award is available to qualified student members of SIGBED (see below for eligibility) and provides funding to attend a SIGSOFT confenrence.  The list of SIGSOFT conferences is available at http://www.sigsoft.org/events.html.  A matching award has been established by SIGSOFT, allowing SIGSOFT student members to attend SIGBED conferences.

    Eligibility

    To qualify for the award, a student must be:
    • author on a paper accepted for presentation at a SIGBED-sponsored conference in the current year or the year before;
    • undertaking research in embedded systems in a graduate program in an accredited college or university at the time of the paper's presentation;
    • a member of SIGBED.

    Application procedure

    The application should be sent by email to Oleg Sokolsky <sokolsky@cis.upenn.edu>, the current SIGBED Secretary/Treasurer, and should consist of:

    - a synopsis of research that the student is pursuing (2 paragraphs, with pointer to at least one publication at a SIGBED sponsored meeting during the year or year before);
    - a proposal to attend a SIGSOFT conference (see http://www.sigsoft.org/) in which the student discusses the potential for crossover in ideas between the student's research and research in software (2 paragraphs limit);
    - an email from the student's research advisor confirming that the student is in good standing and pursuing the research described in the proposal.

    Application deadline

    All applications should be received by August 28, 2016.  The winner will be selected promptly thereafter.  Late applications cannot be guaranteed consideration.

    Selection

    The selection will be done by the SIGBED Executive Committee (Insup Lee, Chair, Eduardo Tovar, Vice-Chair, and Oleg Sokolsky, Secretary/Treasurer) based on the student's research record and relevance to the cross-disciplinary spirit of the award. The award will be presented during the ESWEEK event. The award consists of a certificate and up to $2000 to cover expenses of the student to attend the chosen SIGSOFT meeting during the next year. Contact the SIGBED Executive Committee members for more information.


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  8. 2015 Paul Caspi Memorial Dissertation Award

    The winner of the 2015 award is Marco Zimmerling for his thesis "End-to-end Predictability and Efficiency in Low-power Wireless Networks," which he completed at ETH Zurich.

    The Paul Caspi Memorial Dissertation Award has been established in 2013 in memory of Dr. Paul Caspi (1944-2012). The award recognizes outstanding doctoral dissertations that significantly advance the state of the art in the science of embedded systems. The winner was selected by a committee, chaired by Prof. Wang Yi. 7 nominations for the award have been received from Germany, Sweden, Switzerland, and USA.
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  9. RAW 2016 - Call for Participation
    =========================
    23rd Reconfigurable Architectures Workshop
    May 23-24, 2016
    Chicago, Illinois USA

    Website: http://raw.necst.it/

    Advance Program:
    May 23, 2016:
    - Keynote speech: Reconfigurable Accelerators for Big Data and Cloud
      Speaker: Peter Hofstee - IBM, Austin, TX, USA
    - Social Event Sponsor: TOPIC Embedded Products

    May 24, 2016:
    - Keynote speech
      Speaker: Patrick Lysaght - Xilinx, San Jose, CA, USA
    - Keynote speech: Why the application development on Systems-on-Chip demands a next level programming model
      Speaker: Dirk van den Heuvel - TOPIC Embedded Products, Eindhoven, the Netherlands

    Overview:
    The 23rd Reconfigurable Architectures Workshop (RAW 2016) will be held in Chicago, Illinois USA in May 2016. RAW 2016 is associated with the 30th IEEE International Parallel & Distributed Processing Symposium (IPDPS 2016) and is sponsored by the IEEE Computer Society Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.

    A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand. The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms architectures, applications, technologies and tools, is essential to fully exploit the possibilities offered by reconfigurable computing. The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and practitioners in the area.

    Topics of interest include, but are not limited to:
    Architectures & Algorithms
    · Theoretical Interconnect and Computation Models
    · Algorithmic Techniques and Mapping
    · Run-Time Reconfiguration Models and Architectures
    · Emerging Technologies (optical models, 3D Interconnects, devices)
    · Bounds and Complexity Issues
    · Analog Arrays

    Reconfigurable Systems & Applications
    · Reconfigurable Accelerators (HPC, Bioinformatics, Acceleration Applications in Finance, Data Mining, Big Data, and Analytics)
    · Embedded systems and Domain-Specific solutions (Digital Media, Gaming, Automotive applications)
    · FPGA-based MPSoC and Multicore
    · Distributed Systems and Networks
    · Wireless and Mobile Systems
    · Emerging applications (Organic Computing, Biology-Inspired Solutions)
    · Critical issues (Security, Energy efficiency, Fault-Tolerance)

    Software & Tools
    · Operating Systems and High Level Synthesis
    · High-Level Design Methods (Hardware/Software Co-design, Compilers)
    · System Support (Soft Processor Programming)
    · Runtime Support
    · Reconfiguration Techniques (Reusable Artifacts)
    · Simulations and Prototyping (Performance Analysis, Verification Tools)
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  10. -------------------------------------------------------------------------
    Call for Papers, Tutorials, Workshops
    -------------------------------------------------------------------------
    
    E M B E D D E D    S Y S T E M S    W E E K
    
    Pittsburgh, PA, US, October 2-7, 2016
    www.esweek.org
    
    =========================================================================
             ++  CASES  ++  CODES+ISSS  ++  EMSOFT  ++  IoT Day  ++
                 ++  Symposia  ++  Workshops  ++  Tutorials  ++
    =========================================================================
    
    -------------------------------------------------------------------------
    Embedded Systems Week is . . .
    -------------------------------------------------------------------------
    ESWeek is the premier event covering all aspects of embedded systems
    and software. By bringing together three leading conferences (CASES,
    CODES+ISSS, and EMSOFT), a special IoT Day, several symposia (like
    ESTIMedia, RSP), and hot-topic workshops and tutorials, ESWeek presents
    attendees a wide range of topics unveiling the state of the art in
    embedded systems design and HW/SW architectures.
    http://esweek.org/documents/2016/esweek_flyer.pdf
    Registered attendees are entitled to attend sessions of all
    conference CASES, CODES+ISSS, EMSOFT, and the IoT Day.
    Symposia, workshops and tutorials require separate registration.
    
    -------------------------------------------------------------------------
    Timeline
    -------------------------------------------------------------------------
    - Abstract Submission:                    April 1, 2016
    - Full Paper Submission:                  April 8, 2016 (Firm Deadline!)
    - Workshop & Tutorial Proposals:          April 8, 2016
    - Notification of Final Acceptance:       April 8, 2016
    - Conference:                             October 2-7, 2016
    
    -------------------------------------------------------------------------
    CASES: International Conference on Compilers, Architecture,
           and Synthesis for Embedded Systems
    -------------------------------------------------------------------------
    CASES is a forum where researchers, developers and practitioners exchange
    information on the latest advances in compilers and architectures for
    high performance embedded systems. In addition to our core areas of
    technical interest including embedded system architectures, compilers and
    embedded systems software, memory architectures, architectures targeting
    power, reliability and security, and emerging application domains, we
    especially encourage papers that address architectural synthesis and
    compiler techniques for heterogeneous and accelerator-rich architectures.
    http://esweek.org/documents/2016/cases_cfp.pdf
    
    CASES Program Chairs:
    Siddharth Garg, NYU Polytechnic School of Engineering, US
    Laura Pozzi, University of Lugano, CH
    
    -------------------------------------------------------------------------
    CODES+ISSS: International Conference on Hardware/Software Codesign
                and System Synthesis
    -------------------------------------------------------------------------
    The International Conference on Hardware/Software Codesign and System
    Synthesis is the premier event in system-level design, modeling,
    analysis, and implementation of modern embedded and cyber-physical
    systems, from system-level specification and optimization down to system
    synthesis of multi-processor hardware/software implementations. The
    conference is a forum bringing together academic research and industrial
    practice for all aspects related to system-level and hardware/software
    co-design. High-quality original papers will be accepted for oral
    presentation followed by interactive poster sessions.
    http://esweek.org/documents/2016/codes_cfp.pdf
    
    CODES+ISSS Program Chairs:
    Andreas Gerstlauer, University of Texas at Austin, US
    Andy Pimentel, University of Amsterdam, NL
    
    -------------------------------------------------------------------------
    EMSOFT: International Conference on Embedded Software
    -------------------------------------------------------------------------
    The ACM SIGBED International Conference on Embedded Software (EMSOFT)
    brings together researchers and developers from academia, industry, and
    government to advance the science, engineering, and technology of
    embedded software development. Since 2001, EMSOFT has been the premier
    venue for cutting-edge research in the design and analysis of software
    that interacts with physical processes, with a long-standing tradition
    for results on cyber-physical systems, which compose computation,
    networking, and physical dynamics.
    http://esweek.org/documents/2016/emsoft_cfp.pdf
    
    EMSOFT Program Chairs:
    Petru Eles, Linkoping University, SE
    Rahul Mangharam, University of Pennsylvania, US
    
    -------------------------------------------------------------------------
    IoT Day: Internet of Things: A Holistic Perspective
    (IoT Day is part of CODES+ISSS)
    -------------------------------------------------------------------------
    Recent advances have led to a vision of a future Internet that connects
    diverse physical entities, ranging from commonplace household appliances
    to smart city Infrastructure. This Internet of Things brings challenges
    in research areas including cyber-physical systems, networked sensing,
    wireless networking, and cloud computing. The IoT Day is designed as a
    meeting point for researchers with the purpose of exchanging examples
    of relevant domain challenges and identifying new and exciting
    interdisciplinary research directions via a combination of contributed
    and invited papers, talks and panels.
    http://esweek.org/documents/2016/iot_cfp.pdf
    
    IoT Day Program Chairs:
    Tarek Abdelzaher, University of Illinois, USA
    Jeff Kephart, IBM Research, USA
    
    -------------------------------------------------------------------------
    Paper Process
    -------------------------------------------------------------------------
    This year ESWeek will introduce a two-stage review process in order
    to further increase quality. Papers passing the first stage of reviews
    will be asked to revise their work based on reviewer comments within a
    short time frame of around two weeks. Revised papers will then enter a
    second stage of reviews to decide on final ac-ceptance. For details,
    see http://esweek.org/author-information
    
    -------------------------------------------------------------------------
    Call for Tutorial Proposals
    -------------------------------------------------------------------------
    ESWeek 2016 is looking for high-quality, timely tutorials to enrich its
    technical program. Tutorials offer a unique opportunity where presenters
    can interact closely with attendees and attendees can gain in-depth
    knowledge on a specific topic. Tutorials on all topics related to
    embedded system design, analysis and development are welcome. ESWeek 2016
    tutorials will take place on Oct 2nd, and can be either be half day or
    full day, lecture style or hands on labs. We invite you to submit tutorial
    proposals before the deadline of April 8, 2016.
    http://esweek.org/documents/2016/tutorial_workshop_cfp.pdf
    
    Tutorials Chair:
    Sharon Hu, University of Notre Dame, US
    
    -------------------------------------------------------------------------
    Call for Workshop Proposals
    -------------------------------------------------------------------------
    ESWeek 2016 will host several workshops on Oct. 6/7 and is soliciting
    proposals for new and recurring workshops. ESWeek workshops are
    excellent opportunities to bring together researchers and practitioners
    from different communities to share their experiences in an interactive
    atmosphere and to foster collaboration for new and innovative projects.
    We invite you to submit workshop proposals on any topic related to the
    broad set of research, education, and application areas in embedded systems.
    http://esweek.org/documents/2016/tutorial_workshop_cfp.pdf
    
    Workshop Chair:
    Tulika Mitra, National University of Singapore, SG
    
    -------------------------------------------------------------------------
    Organization
    -------------------------------------------------------------------------
    ESWeek General Chairs:
    Jörg Henkel, KIT Karlsruhe, DE (General Chair)
    Lothar Thiele, Swiss Federal Institute of Technology, Zurich, CH (Vice General Chair)
    ESWeek Local Arrangement Chair:
    Alex K. Jones, University of Pittsburgh, US
    
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