1. ACM SIGBED Early Career Researcher Award:

    Call for Nominations


    ACM SIGBED  (http://sigbed.blogspot.fr/p/about.html) recently established Early Career Researcher Award to recognize contributions by junior researchers in the area of embedded, real-time, and cyber-physical systems. We now encourage SIGBED community members to nominate researchers for the inaugural 2018 award.

    Eligibility:

    The nominee should be a SIGBED member, should have obtained a PhD (or equivalent degree) after January 1, 2011, and have research focus on topics of relevance to SIGBED. See SIGBED webpage for SIGBED sponsored conferences to determine relevance and instructions regarding how to join SIGBED.

    Nomination Process:

    The nomination consists of a letter from the nominator summarizing the nominee's research contributions and explaining its significance and relevance to SIGBED, and two letters of endorsement. All the material should be sent by email to the chair of the award selection committee. Contact the chair for any questions.

    Nomination Deadline: January 15, 2018

    Selection Criteria:

    The award selection committee will review the nomination package and collectively choose the winner based on the significance of the contributions to the SIGBED community. The committee has the option to decline to make the award.

    Award Details:

    The chosen nominee will be notified by February 15, 2018, and the award will be presented by ACM SIGBED Chair at 2018 CPSWeek. The award consists of a plaque engraved with the nominee's name, $1000 honorarium, and upto $2000 towards support for travel to CPSWeek. Funding for the award is provided by ACM SIGBED.

    2018 Award Selection Committee:

    Rajeev Alur (Chair, email: alur@cis.upenn.edu),
    Sanjoy Baruah, Janos Sztipanovits, and Marilyn Wolf

    Conflict of Interest Policy:

    It is possible that members of the selection committee have worked with the nominees and may have a conflict of interest. The nominator should alert the chair about such conflicts. Conflicts of interest shall not automatically prevent a committee member from taking part in the selection process. However, if a member of the committee, or the chair of the committee, feels that the association of a committee member with a nominee would interfere with impartial consideration of the nominees, the member shall be excused from the relevant parts of the discussion. If the same committee member has conflicts with multiple nominees, the Chair of the committee may seek a replacement.
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  2. CALL FOR PAPERS 


    Topic D1: System Specification and Modeling 


    at Design, Automation and Test in Europe (DATE 2018), Dresden, Germany, March 19-23, 2018 https://www.date-conference.com/call-for-papers
     
     
     
    SUBMISSION DEADLINE: Sunday, Sept. 10, 2017. 

    All papers have to be submitted electronically via the conference web page (see https://www.date-conference.com/submission-instructions). 

    General Information 

     
    DATE 2018, will take place from 19 to 23 March, 2018, at the International Congress Center in Dresden, Germany. The conference addresses all aspects of research into technologies for electronic and embedded systems engineering. The conference has a dedicated track for Design Methods and Tools (Track D). This track addresses design automation, design tools and hardware architectures for electronic and embedded systems. The emphasis is on methods, algorithms, and tools related to the use of computers in designing complete systems. The track’s focus includes significant improvements on existing design methods and tools as well as forward-looking approaches to model and design future system architectures, design flows, and environments. 

    We invite you to submit papers to Topic D1: System Specification and Modeling 
     

    Main topics of interest of Topic D1

    Modeling and specification methodologies for complex HW-SW systems; requirements engineering; multi-domain/multi-criteria specifications; meta-modeling; design and specification languages; application and workload models; models of computation and their (static) analysis; concurrency and communication models; model- and component-based design; refinement and validation flows; modeling and analysis of functional and non-functional system properties; performance modeling; timing analysis; predictive and learning-based models; system-level platform and architecture models and simulation. 
     

    Topic members 

     Ingo Sander, KTH Royal Institute of Technology, SE, Topic Chair 
     Andreas Gerstlauer, University of Texas at Austin, US, Topic Co-Chair 
     Patricia Balbastre, Universtat Politecnica de Valencia, ES 
     Michael Hübner, Ruhr-Universität Bochum, DE
     Frederic Mallet, Univ. Nice Sophia Antipolis, FR 
     Gianluca Palermo, Politecnico di Milano, IT 
     Laurence Pierre, TIMA Lab., FR 
     Martin Radetzki, University of Stuttgart, DE 
     Sander Stuijk, Eindhoven University of Technology, NL 
     Jürgen Teich, Universität Erlangen-Nürnberg, DE 
     
     
     Yours sincerely, 

    Ingo Sander and Andreas Gerstlauer 
    DATE Topic D1 Chairs
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  3. Travel Grants for Embedded Systems Week 2017


    A limited number of travel grants to attend ESWEEK 2017 in Seoul, Korea, are available.  Applications are now accepted.  Application rules and procedures can be found on the ESWEEK web site.

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  4. CALL FOR PAPERS

    The Conference on Design and Architectures for Signal and Image Processing

    DASIP 2017

    Desden, Germany, September 27 - 29, 2017

    QUICK LINK: Web site: http://dasip2017.esit.rub.de/index.html

    IMPORTANT DATES:

    • Abstract submission deadline:                            May 25, 2017 (Extended)
    • Paper submission deadline:                                June 1, 2017 (Firm Deadline)
    • Regular paper notification of acceptance:          June 15, 2017
    • Demo Night paper submission:                          June 1, 2017
    • Demo Night papers notification of acceptance: June 30, 2017
    • Camera ready papers:                                         July 15, 2017
    • Symposium Dates:                                             September 27-29, 201
    HIGHLIGHTS:
    • Special Sessions:
      • Signal Processing and Architectures for 5G Wireless Systems
      • Reconfigurable Systems and Tools for Signal, Image and Video Processing
      • SCRAT: Smart CameRAs design and archiTecture
      • Real-time Hyperspectral Image and Video Processin
    • Demo Night:  Universities and public research institutes are invited to demonstrate their hardware platforms, prototypes and tools. Authors should submit their full papers (up to 2 pages, double-column IEEE format) in PDF through the web based submission system. Accepted Demo Night papers containing new scientific results have the option to be submitted for inclusion in the IEEE Digital Xplore Library (To be confirmed).

    DASIP provides an inspiring international forum for latest innovations and developments in the field of leading edge embedded signal processing systems. The conference program will include keynote speeches, contributed paper sessions, demonstrations, and special sessions on timely topics. Authors are invited to submit manuscripts on topics including, but not limited to:

    Design Methods and Tools

    • Design verification and fault tolerance
    • Embedded system security and security validation
    • System-level design and hardware/software co-design
    • Communication synthesis, architectural and logic synthesis
    • Embedded real-time systems and real-time operating systems
    • Rapid system prototyping, performance analysis and estimation
    • Formal models, transformations, algorithm transformations and metrics
    Development Platforms, Architectures and Technologies
    • Embedded platforms for multimedia and telecom
    • Many-core and multi-processor systems, SoCs, and NoCs
    • Reconfigurable ASIPs, FPGAs, and dynamically reconfigurable systems
    • Asynchronous (self-timed) circuits and analog and mixed-signal circuits
    • Digital bio-signal processing, biologically based and/or inspired systems
    Use-Cases and Applications
    • Ambient intelligence, ubiquitous and wearable computing
    • Global navigation satellite systems, smart cameras, and PDAs
    • Security systems, cryptography, object recognition and tracking
    • Embedded systems for automotive, aerospace, and health applications
    • High-level synthesis and design methodologies for heterogeneous, reconfigurable and/orcustom processors/systems
    Smart Sensing Systems
    • Sensor networks, environmental and system monitoring
    • Vision, audio, fingerprint, health monitoring, and biosensors
    • Structurally-embedded, distributed, and multiplexed sensors
    • Sensing for active control systems, adaptive and evolutionary sensors
    Full submission requirements, templates and submission instructions can be found at: http://dasip2017.esit.rub.de/submission.html
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  5. CALL FOR PAPERS

    International Symposium on Highly-Efficient Accelerators and Reconfiguration Technology

    HEART 2017

    Bochum, Germany, June 7-9, 2017

    QUICK LINK: Web site: http://heart2017.esit.rub.de/index.html

    IMPORTANT DATES:
      • Submission deadline for abstracts of conference papers: March 15, 2017
      • Submission deadline for full conference papers: March 19, 2017 (Firm deadline)
      • Submission deadline for design competition papers: March 31, 2017
      • Acceptance notification: April 15, 2017
      • Camera-ready/Author registration: April 30, 2017
      • Symposium dates: June 7-9, 2017
      HIGHLIGHTS:
      • Xilinx Pynq Workshop will be organized on June 6, 2017
      • Social Event: Starlight Express Musical 

      The Eighth International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART) is a forum to present and discuss new research on accelerators and the use of reconfigurable technologies for high-performance and/or power-efficient computation.
      Submissions are solicited on a wide variety of topics related to the acceleration for high-performance computation, including but not limited to:

      Architectures and systems:
      • Novel systems/platforms for efficient acceleration based on FPGA, GPU, and other devices
      • Heterogeneous processor architectures and systems for scalable, high-performance, high-reliability, and/or low-power computation
      •  Reconfigurable and configurable hardware and systems including
        IP-cores, embedded systems, SoCs, and cluster/grid/cloud computing
        systems for scalable, high-performance and/or low-power processing
      • Custom computing system for domain-specific applications such as
        Big-data, multimedia, bioinformatics, cryptography, and more
      • Novel architectures and device technologies that can be applied to efficient acceleration, including many-core/NoC architectures, 3D-stacking technologies and optical devices
      Software and applications:
      •   Novel applications of high-performance computing and Big-data processing with efficient acceleration and custom computing
      • System software, compilers and programming languages for efficient acceleration systems / platforms, including many-core processors, GPUs, FPGAs and other reconfigurable /custom processors
      • Run-time techniques for acceleration, including Just-in-Time compilation and dynamic partial-reconfiguration
      • Performance evaluation and analysis for efficient acceleration
      • High-level synthesis and design methodologies for heterogeneous, reconfigurable and/or custom processors/systems
      In order to encourage open discussion on future directions, the program committee will provide higher priority for papers that present highly innovative and challenging ideas.

      We are planning to organize special sessions on HPC, Big data, and Dynamic Reconfiguration. When submitting a paper, please select topic(s) if the paper is related to them. Note that regardless of the selection of special session topic(s), your paper will undergo the same peer-review process as the main technical track.

      Selected accepted papers will be published in ACM post-proceedings (tentative).



      FPGA Design Contest 2017 (Trax)

      Following the FPGA design competition in HEART2016, we are planning another Trax design  contest at HEART2017. The regulation of this contest will be announced soon.

      Submissions can be made through:

      The HEART2017 paper template can be download here: HEART2017 template in
      MS-Word, HEART2017 template in Latex.

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    • CALL FOR PAPERS
      R T C S A
      THE 23RD IEEE INTERNATIONAL CONFERENCE ON EMBEDDED
      AND REAL-TIME COMPUTING SYSTEMS AND APPLICATIONS
      August 16-18, 2017, Hsinchu, Taiwan


      Important Dates:
      - Paper Submission Deadline: April 14, 2017
      - Acceptance Notification: June 2, 2017
      - Final Paper Submission: June 16, 2017
      - Conference Date: August 16-18, 2017

      RTCSA 2017 is going to be held in Hsinchu, Taiwan and organized by NCTU. The RTCSA conference series carry on with the tradition and bring together researchers and developers from academia and industry for advancing the technology of embedded and real-time systems and their emerging applications, including the Internet of things and cyber-physical systems.

      RTCSA seeks both research and industry track papers that describe research or technical aspects in the area of embedded and real-time systems. Proceedings will be published by the IEEE Computer Society. More information on RTCSA 2017 can be found at http://www.rtcsa.org/

      [Sponsors]
      IEEE Computer Society Technical Committee of Real-Time Systems, IEEE Technical Committee on Cyber-Physical Systems, and Computer Society of the Republic of China.

      [Scopes]
      The 23rd edition of RTCSA will bring together researchers and developers from academia and industry to promote cross-fertilization and discuss advances and trends in the technology of embedded and real-time systems and their emerging applications, including the Internet of Things and Cyber-Physical Systems. RTCSA 2017 seeks
      papers that describe original research in these areas, particularly in:

      **************************
      * EMBEDDED SYSTEMS TRACK *
      **************************
      - Embedded System Architectures
      - Multi-Core Embedded Systems
      - Operating Systems and Scheduling
      - Embedded Software and Compilers
      - Non-Voltaile Memory and Storage
      - Power/Thermal Aware Design
      - Fault Tolerance and Security
      - Sensor-based Systems and Applications
      - Embedded Systems and Design Methods for Cyber-Physical Systems
      - Reconfigurable Computing Architectures and Software Support
      - Ubiquitous and Distributed Embedded Systems and Networks

      ***************************
      * REAL-TIME SYSTEMS TRACK *
      ***************************
      - Real-Time Operating Systems
      - Real-Time Scheduling
      - Timing Analysis
      - Programming Languages and Run-Time Systems
      - Middleware Systems
      - Design and Analysis Tools
      - Communication Networks and Protocols
      - Media Processing and Transmissions
      - Real-Time Aspects of Wireless Sensor Networks
      - Energy Aware Real-Time Methods
      - Real-Time Aspects of Databases

      *********************************************
      * IoT, CPS, AND EMERGING APPLICATIONS TRACK *
      *********************************************
      - Systems, Technology and Foundations of IoT and CPS
      - Applications and Case Studies of IoT and CPS
      - Smart and Connected Health
      - Industrial Internet and Industry 4.0
      - Smart City Technology and Applications
      - Smart Transportation and Infrastructure
      - Cyber-Physical Co-Design
      - Cloud, Middleware and Networks for IoT and CPS
      - Wireless Sensor-Actuator Networks for IoT and CPS
      - Industrial Networks and Systems

      RTCSA 2017 General Chairs:
      - Samarjit Chakraborty, TU Munich, Germany
      - Li-Pin Chang, National Chiao-Tung University, Taiwan

      RTCSA 2017 Program Chairs:
      - Real-Time Systems Track: Bjorn Andersson, CMU, USA
      - Embedded Systems Track: Jen-Wei Hsieh, National Taiwan University of Science and Technology, Taiwan
      - IoT, CPS, and Emerging Applications Track: Luis Almeida, U. Porto, Portugal

      [Paper Submission]
      Both research and industry track papers are solicited. The submitted manuscript must describe original work not previously published and not concurrently submitted elsewhere. Submissions should be no more than 10 pages in the IEEE conference proceedings format (two-column, single-space, 10pt). Conference content will be submitted for inclusion into IEEE Xplore, and will be EI indexed.

      [Work-in-Progress Session]
      This session provides an opportunity for researchers attending RTCSA to present and discuss their latest research and get early feedback from the community at large. More detailed information is available on the web.

      [Special Issues of Journals]
      Selected papers will be recommended for submission of extended versions to the special issues of journals, such as the ACM Transactions on Cyber Physical Systems (application in progress).
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    • CALL FOR PAPERS

      Submission Deadline Extended

      24th Reconfigurable Architectures Workshop
      RAW 2017
      Buena Vista Palace Hotel
      Orlando, Florida, USA, May 29-30 2017

      QUICK LINK: Web site: http://raw.necst.it/

      IMPORTANT DATES:

      Abstract submission: February 2, 2017
      Submission deadline: February 5, 2017 (final)
      Decision notification: March 1, 2017
      Camera-Ready papers due: March 15, 2017

      The 24th Reconfigurable Architectures Workshop (RAW 2017) will be held in Orlando, Florida USA in May 2017. RAW 2017 is associated with the 31st Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2017) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.

      A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand. The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms architectures, applications, technologies and tools, is essential to
      fully exploit the possibilities offered by reconfigurable computing. The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and  practitioners in the area.


      Submissions can be made through:
      . the RAW2017 web site: http://raw.necst.it/
      . EasyChair: https://easychair.org/conferences/?conf=raw2017
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    • Paul Caspi Award 2017


      The ACM SIGBED Paul Caspi Dissertation Award is presented annually to the author of an outstanding dissertation in the area of Embedded Systems.   Nominations are now accepted for the 2017 award.

      The nomination should be submitted via EasyChair at
             https://easychair.org/conferences/?conf=caspiaward17
      by March 1, 2016. For further information,  contact Wang.Yi@it.uu.se

      The author of the winning dissertation will be invited to publish a dissertation summary in the ACM SIGBED Newsletter and to submit their work to the journal ACM TECS (Transactions on Embedded Computing Systems) for possible publication, after the normal peer-review process. The award includes an award certificate for the author and an honorarium of 2000 USD. A public citation for the award paper will be placed on the SIGBED web site.

      Selection Committee
      Christoph Kirsch
      Nikil Dutt
      Tei-Wei Kuo
      Florence Maraninchi
      Oleg Sokolsky
      Reinhard Wilhelm
      Wang Yi (Chair)

      Selection Process

      The award is for an outstanding doctoral dissertation dated within one year preceding the nomination due date. A selection committee and a selection committee chair will be selected by the current SIGBED Executive Committee. A member of the current SIGBED Executive Committee will be one of the selection committee members. The committee chair shall adjudicate conflicts of interest, appointing substitutes to the committee as necessary. Dissertations supervised by a selection committee member are ineligible to be nominated. For purposes of continuity, committee members may remain on the committee for up to three years. The selection committee shall be no less than three persons in size.

      Nomination Process

      A nomination should consist of the following items:
         - Name, address, phone number, and email address of the person making the nomination (the nominator).
         - Name, address, phone number, and email address of the candidate for whom an award is recommended (the nominee).
         - A short statement (200-500 words) explaining why the nominee deserves the award.
         - Supporting statements from up to two persons in addition to the nominator.
         - The nominated dissertation in an English language version.
         - A list of the nominee's publications that were used as the basis of chapters in the nominated dissertation.
         - The CV of the nominee.

      The selection committee will make a recommendation on the winner of the award to the SIGBED Executive Committee, which will approve and announce the final winner. SIGBED Executive Committee members who have conflicts of interest with any nominee will be excluded from the approval process. The primary selection criterion will be the quality of the candidate's work, with the aim to recognize outstanding doctoral dissertations. The selection committee may choose to issue no award in a given year. The award may not be given to multiple recipients.


      For information about the award and the nomination process, see http://sigbed.blogspot.fr/p/awards.html
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    • CALL FOR PAPERS

      International Symposium on Highly-Efficient Accelerators and Reconfiguration Technology

      HEART 2017

      Bochum, Germany, June 7-9, 2017

      QUICK LINK: Web site: http://heart2017.esit.rub.de/index.html

      IMPORTANT DATES:
      Paper submission due: February 20, 2017
      Author notification: April 15, 2017
      Camera-ready due: April 30, 2017
      Symposium Dates: June 7-9, 2017

      The Eighth International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART) is a forum to present and discuss new research on accelerators and the use of reconfigurable technologies for high-performance and/or power-efficient computation.
      Submissions are solicited on a wide variety of topics related to the acceleration for high-performance computation, including but not limited to:

      Architectures and systems:
      • Novel systems/platforms for efficient acceleration based on FPGA, GPU, and other devices
      • Heterogeneous processor architectures and systems for scalable, high-performance, high-reliability, and/or low-power computation
      •  Reconfigurable and configurable hardware and systems including
        IP-cores, embedded systems, SoCs, and cluster/grid/cloud computing
        systems for scalable, high-performance and/or low-power processing
      • Custom computing system for domain-specific applications such as
        Big-data, multimedia, bioinformatics, cryptography, and more
      • Novel architectures and device technologies that can be applied to efficient acceleration, including many-core/NoC architectures, 3D-stacking technologies and optical devices
      Software and applications:
      •   Novel applications of high-performance computing and Big-data processing with efficient acceleration and custom computing
      • System software, compilers and programming languages for efficient acceleration systems / platforms, including many-core processors, GPUs, FPGAs and other reconfigurable /custom processors
      • Run-time techniques for acceleration, including Just-in-Time compilation and dynamic partial-reconfiguration
      • Performance evaluation and analysis for efficient acceleration
      • High-level synthesis and design methodologies for heterogeneous, reconfigurable and/or custom processors/systems
      In order to encourage open discussion on future directions, the program committee will provide higher priority for papers that present highly innovative and challenging ideas.

      We are planning to organize special sessions on HPC, Big data, and Dynamic Reconfiguration. When submitting a paper, please select topic(s) if the paper is related to them. Note that regardless of the selection of special session topic(s), your paper will undergo the same peer-review process as the main technical track.

      Selected accepted papers will be published in ACM post-proceedings (tentative).



      FPGA Design Contest 2017 (Trax)

      Following the FPGA design competition in HEART2016, we are planning another Trax design  contest at HEART2017. The regulation of this contest will be announced soon.

      Submissions can be made through:
      . the HEART2017 web site: http://heart2017.esit.rub.de/index.html
      . EasyChair: https://easychair.org/conferences/?conf=heart2017

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    • CALL FOR PAPERS

      24th Reconfigurable Architectures Workshop
      RAW 2017
      Buena Vista Palace Hotel
      Orlando, Florida, USA, May 29-30 2017

      QUICK LINK: Web site: http://raw.necst.it/

      IMPORTANT DATES:
      Abstract submission January 11, 2017
      Submission deadline January 15, 2017
      Decision notification  February 17, 2017

      The 24th Reconfigurable Architectures Workshop (RAW 2017) will be held in Orlando, Florida USA in May 2017. RAW 2017 is associated with the 31st Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2017) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.

      A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand. The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms architectures, applications, technologies and tools, is essential to
      fully exploit the possibilities offered by reconfigurable computing. The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and  practitioners in the area.


      Submissions can be made through:
      . the RAW2017 web site: http://raw.necst.it/
      . EasyChair: https://easychair.org/conferences/?conf=raw2017

      KEYNOTE
      Ronald F. DeMara, Director of Computer Architecture Laboratory, University of Central Florida
      Georgi Gaydadjiev, VP of Dataflow Software Engineering, Maxeler Technologies Ltd

      TOPICS OF INTEREST

      Hot Topics in Reconfigurable Computing
      • Configurable Cloud
      • Heterogeneous Computing in Data Centers
      • Accelerating Data Center Workloads
      • FPGA-based Deep Learning
      • Accelerating Genomic Computations
      • Acceleration of Data Analytics
      • Reconfigurable Computing in the IoT era
      • Organic Computing, Biology-Inspired Solutions
      • Applications in Finance

      Architectures & CAD
      • Algorithmic Techniques and Mapping
      • Emerging Technologies (optical models, 3D Interconnects, devices)
      • Reconfigurable Accelerators
      • Embedded systems and Domain-Specific solutions (Digital Media, Gaming, Automotive applications)
      • FPGA-based MPSoC and Multicore
      • Distributed Systems & Networks
      • Wireless and Mobile Systems
      • Critical issues (Security, Energy efficiency, Fault-Tolerance)

      Runtime & System Management
      • Run-Time Reconfiguration Models and Architectures
      • Autonomic computing systems
      • Operating Systems and High-Level Synthesis
      • High-Level Design Methods (Hardware/Software co-design, Compilers)
      • System Support (Soft processor programming)
      • Runtime Support
      • Reconfiguration Techniques
      • Simulations and Prototyping (performance analysis, verification tools)
      For more information see: http://raw.necst.it/
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